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Transistor. Both of these factors contribute directly to sense amp speed. Note that because of the relatively poor performance of CMOS differential pairs, fast CMOS designs rely instead on positive-feedback clocked sense amps, which require special critical timing pulses for both equilibration and sensing. Sense Amps and Data Lines Bipolar transistors make nearly ideal sense amps because of their low mismatch (typically much less than 1 mV with proper layout) and exponential current–voltage relationship.
Two ECL NOR gates with emitter-follower current sharing: (a) diode, (b) active (3). The current sharing permits each decoder to be powered up for maximum speed without exceeding the overall memory’s power budget. Reprinted with permission from ‘‘A Subnanosecond 64kb BiCMOS SRAM,’’ Santoro, Tavrow, and Bewick, Proc. BCTM. 1994 IEEE. BiCMOS MEMORY CIRCUITS performance. Despite significant efforts by many groups (15), true active pull-down circuits remain fickle. They are either process intolerant or require special devices or supply voltages.
3 V CMOS generation, the ECL circuits must be limited to a modified two-level series-gated approach. 3 V CMOS is possible, with the lower voltage either supplied externally or generated internally. 3 V CMOS generation, mixed-supply circuits become necessary. Typically for ECL BiCMOS, the CMOS is referenced to the lower ECL supply (2, 3) because the n–p–n transistor cannot pull up all the way to the upper supply; however, referencing to the upper supply also has some advantages (4). BiCMOS PROCESS CONSIDERATIONS Vdd Vdd Vdd In gnd In gnd Out gnd gnd Out gnd mBiCMOS BiNMOS gnd gnd gnd R2 Vb1 In Out Vcsf Vcs R3 R1 Veef Vee ECL Figure 1.